In many digital communication systems, phase-locked loop (PLL) circuits are employed in applications such as clock synthesis and/or clock or data signal recovery (e.g., from a nonreturn-to-zero (NRZ)-encoded high speed serial data stream). Referring now to FIG. 1, a block schematic diagram shows a conventional PLL circuit 100 using a phase detector to compare a clock output to a reference clock. Phase detector 102 can receive a reference clock and a clock output, while providing up/down controls 104 to charge pump 106. Voltage controlled oscillator (VCO) 110 can receive an input voltage or frequency control signal VIN from charge pump 106 and/or loop filter 108, and provides the clock output.
Such VCOs are typically used in PLL applications, and may be implemented in application-specific integrated circuit (ASIC) designs, for example. Further, modern ASICs using several different clock domains may need a corresponding number of clock generators. For example, where the clock domains may not be integral with each other (e.g., no frequency divider can produce a specific, related frequency), a separate PLL may be needed. In many cases, the time range in which such clocks are generated can be from hundreds of kHz to the GHz range. Thus, the physical design or layout may require different PLLs to cover each different frequency range.
Accordingly, a drawback of conventional VCO and PLL design approaches is that two or more separate VCOs may be needed to cover a relatively wide frequency spectrum. Such designs can increase die area, thus resulting in increased associated costs. However, an efficient circuit and/or approach for increasing the frequency range of a VCO could provide advantages over a conventional two-VCO approach.